1. Field of the Invention
This invention relates to the field of integrated circuit chip packaging, and more specifically to packaging semiconductor chips on a substrate comprised of multilayer thin and/or thick (e.g. multilayer ceramic or organic) films.
2. Description of Related Art
U.S. Pat. No. 4,866,507 of Jacobs et al. for xe2x80x9cModule for Packaging Semiconductor Integrated Circuit Chips on a Base Substratexe2x80x9d describes a structure with alternating insulating and conductive layers formed on a substrate. Some of the conductive layers are patterned to have substantially coplanar spaced apart power/ground lines and signal lines on each layer with interconnections between power/ground lines on different levels forming a power/ground plane at the appropriate voltage level in three dimensions.
In accordance with this invention a semiconductor carrier and a corresponding method for forming the carrier are provided for interconnecting ground, signal and power lines in a semiconductor carrier. The method of forming the carrier of this invention involves forming a stack of a plurality of insulating layers with generally parallel conductor lines including power lines and ground lines formed in planes therebetween with the generally parallel lines directed in orthogonal directions between any two of the insulating layers with alternation between planes of X-directed lines and planes of Y-directed lines and power lines and ground (reference potential) lines (networks) formed in parallel in a single plane. Form Z-directed via connections between planes connecting a power line in one plane to another power line in another plane. Form Z-directed via connections between planes connecting a ground line in a first plane to another ground line in a second plane, and form a signal line located between a ground line and a power line in a given plane and form a continuing X-directed and/or Y-directed line segment(s) of the signal network (net) in another plane between different ground and power lines.
The signal line and the continuing line segment are connected by one or more Z-directed vias passing through at least one insulating layer.
In another aspect of the invention it is necessary that the signal line and the continuing line segment are connected by a via passing through at least one insulating layer and preferred that the signal line is between a power line and a ground line and the continuing line segment is between another power line and another ground line.
Preferably, a coplanar group of ground, power and signal lines are formed in parallel in a single plane in a surface of one of the insulating layers.
Preferably, the signal line and the continuing line segment are connected by a via passing through at least one insulating layer.
Preferably, the signal line is between a power line and a ground line and the continuing line segment is between another power line and another ground line.
Preferably, a coplanar group of ground, power and signal lines are formed in parallel in a single plane in a surface of one of the insulating layers between a layer of top surface metallurgy (TSM) on top and a layer of bottom surface metallurgy (BSM) on the bottom.
Preferably, there are vias directed along the vertical Z axis interconnecting respective power, ground and signal lines.
The concept of this invention is independent of whether thin or thick multilayers are used, but its actual thick film ceramic hardware embodiment is important for proving the robustness and ease of applicability of the concept, not to overlook the importance of proving the feasibility of applying the idea.